library verilog;
use verilog.vl_types.all;
entity ALU is
    port(
        ALUctrl         : in     vl_logic_vector(2 downto 0);
        data1_in        : in     vl_logic_vector(31 downto 0);
        data2_in        : in     vl_logic_vector(31 downto 0);
        data            : out    vl_logic_vector(31 downto 0);
        zero_flag       : out    vl_logic
    );
end ALU;
